A 1.35 GHz CMOS wideband frequency synthesizer for mobile communications

The design and simulation of a 1.35 GHz fully integrated CMOS frequency synthesizer for a double band receiver is presented. The proposed synthesizer is based in a wide-band PLL topology with a high reference frequency. This approach allows obtaining low phase noise, fast switching time, a low divider ratio and a reduction in the total chip area. Besides, the use of a novel charge-pump circuit with partial positive feedback and current reuse allows a further reduction in both chip area and power consumption, making the proposed structure suitable for high frequency and low-voltage phase-locked loops. Key-Words: Frequency synthesizers, ring oscillators, mixed-mode circuits, wireless integrated circuits.